Flash electrically programmable read only memories ("EPROMs") and flash electrically erasable and programmable read only memories ("EEPROMs") are solid state devices that can persistently store digital data. As shown by FIG. 1, an EPROM-type flash cell 10 typically has a metal-on-silicon ("MOS") structure that includes a substrate 12, source and drain regions 14, 16, a floating gate 18 overlying MOS channel region 20 but separated therefrom by a thin layer region 22 of oxide 24. A control gate 26 is formed overlying floating gate 18. For a flash EPROM, it is necessary to surround the source region with a lightly doped region 15 of like-conductivity type dopant. The substrate or bulk 12 is tied to a potential Vbb that typically is ground.
For the NMOS device depicted, substrate 12 is doped with P-type impurities, and the source and drain regions are doped with N-type impurities. For a flash EPROM, N+ source region 14 is surrounded by an N- region 15. The N- region 15 is included to protect the source junction from the large source-floating gate electric field used to electrically erase the cell. This N- region helps reduce electric field magnitude between source nodes and the first polysilicon layer (not shown) during erase operations.
Of course a PMOS device may be formed by substituting an N-type substrate, and P-type source, drain regions. Generally, NMOS devices are preferred to PMOS devices in that the majority carriers in NMOS devices, electrons, have 2.5 times the mobility of the majority carriers, holes, in PMOS devices, and thus can operate more rapidly. Although an EPROM-type flash cell is depicted, it is to be understood that the present invention may also be used with EPROM, or EEPROM type memory as well.
A Vcg voltage coupled to control gate 26 can affect charge stored on floating gate 18, which charge affects the Vt threshold voltage of MOS device 10. The magnitude of charge on the floating gate controls the minimum (or Vt) voltage Vcg that will turn-on device 10, causing drain-source current to flow across the channel region 20. Device 10 is programmed to one of two states by accelerating electrons from substrate channel region 20 through the thin gate dielectric 22 region onto floating gate 18.
The state of device 10, e.g., how much charge is stored on floating gate 18, is read by coupling an operating voltage Vds across source and drain regions 14, 16. The drain-source current Ids is then read to determine whether data stored in the device is a logic level one or zero for a given control voltage level Vcg. The two logic states may be differentiated by sensing relative current levels, e.g., perhaps 100 .mu.A versus 10 .mu.A.
Two mechanisms are in common use to program a flash EPROM (or to erase a flash EEPROM, whose definitions of erasing and programming are opposite), namely channel-hot-electron ("CHE" ) injection, and Fowler-Nordheim ("FN") tunnelling. Commonly, EPROM-flash devices use FN-erase mode and CHE-program mode operations, which combination is sometimes referred to as ETOX, for EPROM tunnel oxide technology. On the other hand, EEPROM-flash devices commonly use FN-erase mode, and FN-program mode operations.
Table 1 summarizes the application of FN and CHE modes, as well as typical cell voltages for gate, source and drain nodes. As described later herein, the present invention is directed to a medium high voltage pump that can increase a lower Vdd voltage to approximately 5 VDC at high current for coupling to the source or drain of cells to be erased or programmed.
TABLE 1 ______________________________________ ERASE PROGRAM ______________________________________ EPROM- FN: CHE: flash G = -8 V, S = 5 V, D = float G = 8 V, S = 0 V, D = 5 V EEPROM- FN: FN: flash G = 15 V, S = 0 V, D = 0 V G = -8 V, S = 5 V, D = float ______________________________________
Thus, for the EPROM-flash cell depicted in FIG. 1, channel-hot-electron injection is used to program the cell to an off-state in read mode. Using CHE technology, it is necessary to apply a positive high voltage Vcg, e.g., perhaps +8 VDC to +10 VDC to control gate 26, while applying perhaps +5 VDC to drain 16, and 0 VDC to source 14. As hot electrons are accelerated and travel from source to drain, the electric field created by the high Vgs and Vds voltages can pull some hot electrons from the drain to the floating gate. (No electrons will be pulled to the floating gate from the source, which is at ground potential.) When using CHE injection, the drain-source channel current will be approximately 0.5 mA/cell.
Using FN technology, an EPROM-flash cell is erased by coupling perhaps -8 VDC to the control gate 26, +5 VDC to the source, and allowing the drain to float. FN-mode erasing can be accomplished with a tunnel current of approximately 10 nA/cell. (Although one can erase an EPROM-flash cell by providing positive high voltage to the source and grounding the control gate, so doing increases source region junction leak current, and increases hot-hole injection at the source region.)
To program an EEPROM-flash cell using FN technology requires applying approximately -8 VDC to control gate 26, applying +5 VDC to source 14, and floating drain 16. The negative Vcg high voltage and Vs produce a large tunnel electric field that can push electrons from the floating gate 18 to the source 14. (No electrons are pulled out of the floating gate to the drain, as the floating drain will not generate a large electric field.) Unfortunately, this causes hole trapping, and degrades the storage capability and endurance of the memory cell. To erase an EEPROM cell using FN technology, approximately +12 VDC is applied to control gate 26, while drain 16 and source 14 are grounded. As was the case for an EPROM-flash cell, FN erasing can be accomplished with a tunnel current of approximately 10 nA/cell.
Typically the circuitry with which memory cells 10 are used is powered by a single low voltage power supply, a 3.3 VDC battery for example, although batteries ranging from perhaps 1.2 VDC to 5 VDC or higher may instead be used. Positive and negative high voltage pump circuits are commonly used to generate the .+-.12 V (V.sub.pp, V.sub.Pn) or so high voltage necessary to program and erase memory cells from a single lower voltage power supply. In the prior art, separate medium voltage pump circuits are used to generate the +5 V or so (V.sub.Pm) that must be supplied at relatively higher current levels in the few mA range. Usually the source shares a pump circuit with the drain, as the voltages required are the same but are used during different operation modes.
From the foregoing discussions of CHE and FN mechanisms, it will be appreciated that the number of cells that can be erased or programmed in parallel, e.g., simultaneously (or in a "flash"), will often be determined by the pump circuit current output characteristics. For example, if a medium voltage V.sub.Pm pump circuit can provide an average 8 mA output current drain-source, 16 bits can be programmed simultaneously, whereas 100 Kbytes may be erased simultaneously.
Understandably, in designing pump circuits it is important that sufficient program or erase current be provided to at least meet the cell requirements to maintain erasing and programming efficiency. In a system with a 5 VDC power supply (Vdd=5 VDC), 32-bit programming can be achieved, but if Vdd=3 VDC, only 8-bit programming can presently be achieved. It simply is difficult in ETOX systems to provide sufficient 0.5 mA/cell program current at 5 VDC drain voltage when Vdd is less than about 3 VDC. Further, it is necessary to pump a 3 VDC Vdd up to 5 VDC, preferably using an on-chip pump circuit, to even meet the 0.5 mA/cell programming requirements. If an externally created 5 VDC Vdd is available, it may of course provide multiple byte-programming, e.g., four-byte, without recourse to an on-chip high current pump. At present, FN-programming dominates sub-3 VDC Vdd systems, whereas CHE-programming dominates 5 VDC Vdd flash memory systems.
However, in some systems an external source of Vpp may be provided, in which case there is no need to provide an on-chip positive voltage Vpp pump. The presence of an external Vpp supply can result in faster and more efficient erase and program mode operations. Although modern flash memory systems can be operated from a variety of power supplies and power supply values, such systems do not include an on-chip Vdd and Vpp voltage detector. For example, such a Vdd/Vpp detector could be used to disable the Vpp pump circuitry of a generic on-chip system that included a positive voltage Vpp pump, thus conserving operating power.
As shown in FIG. 2, it is common to form an integrated circuit ("IC") 100 that includes a plurality of cells 10 that are arrayed in addressable rows and columns that define a storage array 110. Address logic 120 permits accessing a specific cell in such an array. For example, during a program/read or erase operation, a given cell 10 may be accessed by applying the proper Vgs, Vd, Vs potentials to all cells in a column containing the addressed cell, and to the row containing the addressed cell.
Commonly, a horizontal row of cells having their control gates tied-together defined a word line ("WL"), whereas a vertical column of cells having their drains tied-together define a bit line ("BL"). Source leads in a block of cells are tired-together to define a source line ("SL"). Changing the WL, BL, SL potential for a selected group of cells enables those cells to be programmed or erased or verified. For ease of illustration, address logic 120 is shown as having a single output lead, but in practice there will be multiple output leads, including leads for Vgs, Vd, and Vs.
In typical arrays, the gate node of cells 10 are coupled to a WL by a polysilicon conductor, as zero DC current will be carried by the WL. The cell drain nodes are coupled to a typically metal BL, and the source nodes are coupled to a SL, typically via an N+ diffusion. Whereas the WL carries zero DC current, the BL may carry a total 5 mA DC if eight cells in the same WL are simultaneously programmed. Further, a SL may carry upwards of 5 mA DC current if 64 Kbytes of cells are collectively erased simultaneously.
The WLs are coupled to a row-selected device by an row decoder (or X-decoder), which for ease of illustration may be assumed to be associated with address logic unit 120 in FIG. 2. The BLs are coupled to a column-selected device driven by a column decoder (or Y-decoder), which is assumed to be associated with address logic 120. The SLs are coupled to source control circuit, assumed to be associated with address logic unit 120. If array 120 includes 1 Mbit of flash memory cells, there will be 1,024 WLs and 1,024 BLs configured in horizontal rows and vertical columns.
In FIG. 2, IC 100 preferably operates from a single low voltage power supply Vdd, perhaps a 5 VDC battery, although the trend has been toward Vdd values of 3.3 VDC or 2.5 VDC, with a goal of perhaps 1.2 VDC.
To generate the high voltage necessary to program or erase the various cells from a lower voltage Vdd supply, voltage pump circuits are used. IC 100 will commonly include a positive high voltage pump circuit 130 that outputs a high positive potential V.sub.pp, and a negative high voltage pump circuit 140 that outputs a high negative potential V.sub.Pn. A medium voltage circuit 145 is also used to output a medium high voltage V.sub.Pm, perhaps +5 V at relatively higher current levels, e.g., .apprxeq.5 mA, than are associated with voltages V.sub.pp and V.sub.Pn.
Because the various pump output voltages are not especially well regulated, voltage regulator circuits 132, 142, 147 are also provided. Typically these circuits employ a constant voltage reference such as a bandgap generator. The output voltages from the voltage regulators will be logically presented to selected groups of cells to provide WL, BL, SL potentials as required by the various modes of operation, as exemplified by the values shown in TABLE 1.
Unfortunately, although regulators 132, 142, 147 may do an acceptable job of regulating voltage at the output ports of the voltage regulators, the WL, BL, SL voltages may not be especially well regulated where the voltages are needed: at the gate, drain, and source nodes of the selected memory cells. Such feedback as is used by prior art regulators 132, 142, 147 is typically internal to regulator itself, e.g., a scaled proportion of the voltage at the output port of the regulator is compared to the reference voltage and the output port voltage is adjusted accordingly. However, feedback from the nodes whereat the voltage should be tightly regulated (e.g., the cell nodes) is not employed.
Many factors contribute to variations in WL, BL, and SL potentials as they appear at the nodes of the selected cells. In practice, WL regulation is less troublesome than BL and SL regulation. Because the WL is coupled to the control gate nodes of selected memory cells, no DC current is drawn. However, WL voltage can vary in verification mode due to device body-effect coupling at the X-decoder. The result is that WL voltage varies due to threshold Vt shifts. In contrast to the minimal WL current requirements, BL and SL may each carry perhaps 5 mA of DC current. Ohmic I.times.R type losses in the BL and SL conductive lines from the regulator outputs to the selected array cell nodes can degrade quality of the voltage regulation, and thus reliability of a program or erase operation.
The voltage-changing effects of parasitic active resistances and column select devices can vary from one select path to another, further causing variations in the voltages actually seen by the selected cells. Temperature variations and fabrication process variations can result in some individual memory cells 10 being erased or programmed more effectively within a given amount of time by the WL, BL, SL potentials seen by the cells, than other cells. Essentially, the erase and program currents required can vary from cell to cell. Further, a cell's program and erase Vt can dynamically vary over time during program and erase operations, which will affect current in that cell.
The above-enumerated factors and other uncontrollable effects contribute to make the voltages actually seen at the drain and source nodes of selected memory cells difficult to reliably predict. Consequently, program and erase operations can be unduly stressful to the memory array, and efficiency of such operations will be degraded, to the detriment of product life of the memory system. Thus, it is common to provide a verify mode to confirm effectiveness of an erase or program operation.
For example, in program verifying mode, potential for the selected WL may be about +2 V for a low threshold voltage ("Vt") memory cell, and perhaps +6 V for a high Vt memory cell. In program verifying mode, the BL will be about +1 V, and the SL will be grounded (for 5 V Vdd operation).
In erase verifying mode, the selected WL is set to +3 V to verify Vt for the cell after erasure, while the WL is set to +1 V to verify cell Vt following erase repair operation.
Table 2 below recapitulates the various BL, WL, and SL potentials commonly encountered, although larger magnitude potentials may also be found.
TABLE 2 ______________________________________ BL (drain) WL (gate) SL (source) ______________________________________ Erase: floating -8 V +5 V Program: +5 V +8 V 0 V Erase verify: +1 V +3 V 0 V Reading: +1 V +Vdd 0 V Program verify: +1 V +6.5 V 0 V Erase repair: +5 V &gt;+1 V 0 V ______________________________________
However, the efficiency of program and erase and verify mode operations is dependent upon the accuracy with which the various programming, erasing, or verifying voltages can be maintained, as seen by the selected cell gate, drain, and source leads. Maintaining a well regulated voltage is especially important for read and verify modes. However, as noted, prior art voltage regulation schemes as shown in FIG. 2 do not actually regulate the WL, BL, SL potentials at the memory cell nodes. Accurately regulating WL, BL, SL potentials becomes more critical as MOS device sizes become smaller. For example, in the past, 1 .mu.m MOS devices could tolerate perhaps .+-.10% tolerance or so on the magnitude of these voltages. But for modern 0.3 .mu.m MOS devices, the same 10% tolerance, especially when combined with other variations, can push the MOS devices beyond acceptable tolerances. Thus, it is especially important to regulate WL, BL, and SL potentials as device sizes continue to shrink.
Understandably, applying too much potential to a WL, BL, SL can stress if not destroy memory cells. On the other hand, under potential can result in false reads and incomplete erasures. Thus, efficient programming, erasing, and verifying a memory array requires tightly control WL, BL, and SL potentials, at the cell nodes coupled to these lines.
IC 100 also includes a phase generator circuit 125 that outputs a plurality of non-overlapping different phase pulse trains (here denoted .phi.1, .phi.2, .phi.3, .phi.4) that drive the positive and negative pump circuits 130, 140, 145.
In typical flash memory applications, an erase time of 1 second is regardless of the number of flash memory cells, e.g., cells 10, being erased. However, in practice, the magnitude of the erase current can limit the number of cells or memory bits that can be erased simultaneously. A typical flash memory cell, e.g., cell 10, may require about 10 nA during erase mode operation, and about 0.5 mA during program mode operation. Stated differently, programming current required by a typical memory cell exceeds erase current by about 50,000:1. Because of this current limitation, it is common to block erase 64 Kbits simultaneously, while programming is directed to one byte (e.g., 8 bits) at a time. Typically, to program a byte requires about 0.5 mA/cell.times.8 cells.apprxeq.4 mA at about 5 VDC. Approximately the same current is required to erase a block of 64 KBytes, e.g., 10 nA/cell.times.64 KByte cells.apprxeq.5 mA. Since simultaneous block erase and byte programming would not occur, a single medium voltage pump circuit capable of approximately 5 mA output at V.sub.Pm can suffice.
It will now be appreciated reliable program, erase, and verify operations require tightly regulate WL, BL, SL potentials at the selected memory cell gates, drains, and sources. However from the foregoing it is apparent that prior art approaches have regulated these potentials tightly at the output port of the various voltage regulators, without accounting for variations in these regulated potentials downstream from the regulator output ports.
However, such regulation as is carried out in the prior art leaves much to be desired. For example, Tedrow et al. in U.S. Pat. No. 5,546,042 discloses a voltage regulator for flash memory in which a resistor divider scales-down the regulated voltage to a level appropriate for a voltage comparator. Unfortunately, the resistor divider draws DC current, which can not readily be spared from the pump circuit whose voltage is being regulated. Further, the divider attenuates changes in the regulated voltage, degrading gain of the regulation system such that a precise voltage at the output of the voltage comparator does not ensure a precise output voltage. What would be more desirable is a regulation method that did not draw DC current, and that could pass to a voltage comparator input essentially all (rather than a fraction of) change in the pump voltage to be regulated.
Although U.S. Pat. No. 5,291,446 to Van Buskirk et al. discloses regulation of a positive potential using capacitive voltage division, Van Buskirk's voltage division also down-scales the error or delta component on the voltage being divided, thus reducing overall regulation efficiency. Further, error occurs in Van Buskirk's capacitor division due to leakage currents. Buskirk also generates a first program mode output and a second program-verify mode output, by changing the capacitor-divide ratio. This approach requires an extra capacitor, and becomes less efficient if multiple output voltage levels are required. What would be more useful would be a regulator in which programmable references create programmable output potentials.
U.S. Pat. No. 4,858,186 to Jungroth discloses an open loop circuit for providing a load for charging an EPROM cell. Jungroth does not use a comparator to detect differences between a reference and the desired regulated voltage, but instead directly applies a fixed control voltage to a source follower whose output is to control selected BL voltage. Unfortunately, if BL potential is too low, Jungroth cannot compensate. Jungroth attempts to use a reference column to generate a fixed control voltage. An assumption is made that the reference column should mimic the selected BL, and that by setting reference column voltage and current to desired values, the selected BL should follow suit. However this scheme is deficient because the circuit and layout of the reference column differ substantially from the BL; for example, the reference column has no memory cell (whose channel current can vary 10:1 during programming, to significantly alter BL potential). As a result, relatively poor BL voltage regulation is provided by this prior art approach.
In summary, there is a need for a system of regulation of WL, BL, and SL potentials that provides the necessary regulation where it is needed, at the gate, drain, and source leads of the selected memory cells. Preferably the voltages delivered at these nodes should be regulated so as to be substantially independent of process and fabrication variations, ambient temperature variations, and Vcc or Vdd power supply variations. In achieving these design goals, preferably a measure of the desired voltage at the selected cell nodes should be taken and fedback to the appropriate voltage regulator.
Since an array can include thousands of BLs and SLs, a mechanism for detecting and regulating only the cell node potentials for the selected BLs and SLs should be implemented to save IC chip area required by the implementation. Because modern flash memory systems can be operated from a variety of power sources, there is a need for a system that includes an on-chip Vdd and Vpp voltage detector. On-chip detection of Vdd and Vpp can help fine-tune performance of on-chip regulators. For example, amplitude of the phase generated clock pulses may vary substantially with Vdd power supply variation, and the ability to detect Vdd and fine-tune on-chip pump voltages accordingly can be advantageous. Further, on-chip detection of Vdd and Vpp may be used to disable on-chip voltage pumps, e.g., a Vpp pump, that need not be operated because the system environment provides the necessary magnitude of Vpp. An on-chip Vpp detector could sense the presence of an external source of Vpp and provide a control signal disabling an on-chip Vpp voltage pump.
The present invention provides such a voltage regulation system.